URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [default.cfg] - Rev 437

Rev	Log message	Author	Age	Path
434	Work in progress with new Ethernet TUN/TAP interface.	jeremybennett	5092d 10h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5283d 14h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5311d 12h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg