OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [default.cfg] - Rev 458

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
458 or1ksim testsuite updates julius 5073d 18h /openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5112d 05h /openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5303d 08h /openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5331d 06h /openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.