OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [inst-set-test.exp] - Rev 123

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5280d 09h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
122 Added l.ror and l.rori with associated tests. jeremybennett 5281d 05h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5281d 06h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5282d 02h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5284d 05h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5285d 05h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5285d 06h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5286d 05h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5289d 06h /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.