OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [ChangeLog] - Rev 232

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
230 Changed library interface. Fixed namespace problems with instruction lookup in library.

* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
jeremybennett 5220d 15h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5252d 19h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
134 Updates for stable release 0.4.0 jeremybennett 5260d 23h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
127 New config option to allow l.xori with unsigned operand. jeremybennett 5266d 19h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5267d 15h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5267d 19h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
122 Added l.ror and l.rori with associated tests. jeremybennett 5268d 15h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5268d 16h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5269d 13h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5271d 16h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5272d 15h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5272d 17h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5273d 15h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
110 or1ksim make check should work without a libc in the or32-elf tools julius 5274d 17h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5276d 16h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
104 Candidate release 0.4.0rc4 jeremybennett 5279d 23h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5294d 19h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5315d 16h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5322d 16h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.