| Rev |
Log message |
Author |
Age |
Path |
| 236 |
Terminate execution on NOP_EXIT, even if debugging, add support for RSP qAttached packet, stall in library after single instruction is ST bit is set in SPR DMR1. Fix softfloat to allow compilation with -O0 for debugging.
* configure: Regenerated.
* configure.ac: Version changed to current date. Test for
varargs.h dropped.
* cpu/or32/insnset.c <l_nop>: Terminate execution on NOP_EXIT,
even if debugging.
* debug/rsp-server.c (rsp_query): Added support for qAttached
packet.
* libtoplevel.c (or1ksim_run): Stall after a single instruction if
SPR_DMR1_ST flag is set.
* softfloat/host.h: Make #define of INLINE conditional, to allow
the user to override.
* softfloat/README: Added instructions for non-optimized compilation.
* softfloat/softfloat-macros: Add a conditional #ifndef
NO_SOFTFLOAT_UNUSUED around unused functions. |
jeremybennett |
5212d 00h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 234 |
Minor tidy ups. DOS end of line chars fixed. |
jeremybennett |
5213d 06h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 230 |
Changed library interface. Fixed namespace problems with instruction lookup in library.
* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int. |
jeremybennett |
5214d 22h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 143 |
Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). |
jeremybennett |
5247d 02h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 134 |
Updates for stable release 0.4.0 |
jeremybennett |
5255d 05h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 127 |
New config option to allow l.xori with unsigned operand. |
jeremybennett |
5261d 02h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 124 |
Overflow handling now in line with architecture manual. Tests added. |
jeremybennett |
5261d 21h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 123 |
Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. |
jeremybennett |
5262d 01h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 122 |
Added l.ror and l.rori with associated tests. |
jeremybennett |
5262d 21h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 121 |
Adds exception handling to l.jalr and l.jr. Adds appropriate tests. |
jeremybennett |
5262d 22h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 118 |
New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. |
jeremybennett |
5263d 19h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 116 |
Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. |
jeremybennett |
5265d 22h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 115 |
Added support for l.fl1 and tests for l.ff1 and l.fl1 |
jeremybennett |
5266d 22h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 114 |
l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. |
jeremybennett |
5266d 23h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 112 |
Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. |
jeremybennett |
5267d 22h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 110 |
or1ksim make check should work without a libc in the or32-elf tools |
julius |
5268d 23h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 107 |
New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. |
jeremybennett |
5270d 22h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 104 |
Candidate release 0.4.0rc4 |
jeremybennett |
5274d 06h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 98 |
Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. |
jeremybennett |
5289d 01h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 93 |
Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. |
jeremybennett |
5309d 23h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
