OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [ChangeLog] - Rev 222

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5279d 03h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
134 Updates for stable release 0.4.0 jeremybennett 5287d 07h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
127 New config option to allow l.xori with unsigned operand. jeremybennett 5293d 03h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5293d 23h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5294d 03h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
122 Added l.ror and l.rori with associated tests. jeremybennett 5294d 23h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5295d 00h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5295d 21h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5298d 00h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5299d 00h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5299d 01h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5299d 23h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
110 or1ksim make check should work without a libc in the or32-elf tools julius 5301d 01h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5303d 00h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
104 Candidate release 0.4.0rc4 jeremybennett 5306d 07h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5321d 03h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5342d 00h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5349d 00h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.