OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [configure] - Rev 582

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
556 or1ksim - added performance counters unit and test for it. julius 4951d 14h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4979d 18h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
532 Ensure the halted flag is cleared when the processor is unstalled. jeremybennett 4990d 15h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
510 Updates for release 0.5.1rc1. jeremybennett 5010d 22h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 5011d 22h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 5053d 15h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5077d 00h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5103d 23h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
458 or1ksim testsuite updates julius 5105d 03h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5113d 18h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5124d 17h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
440 Updated documentation to describe new Ethernet usage. jeremybennett 5131d 13h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5140d 08h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5143d 14h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
432 Updates to handle interrupts correctly. jeremybennett 5144d 18h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 5150d 13h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 5158d 18h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 5158d 21h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5198d 19h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.		 jeremybennett 5223d 21h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.