OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [inst-set-test/] [inst-set-test.S] - Rev 867

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
787	Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k: 2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com> Patch from R Diez <rdiezmail-openrisc@yahoo.de> * cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S, * except/except.S, ext/ext.S, flag/flag.S, fp/fp.S, * inst-set-test/inst-set-test.S, int-test/int-test.S, * mc-common/except-mc.S, uos/except-or32.S: Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero, and indeed it is not when simulating the or1200 Verilog core. * configure: Regenerated. * configure.ac: Updated version.	jeremybennett	4657d 05h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
121	Adds exception handling to l.jalr and l.jr. Adds appropriate tests.	jeremybennett	5304d 21h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
118	New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library.	jeremybennett	5305d 18h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5307d 21h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5312d 22h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.