URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [int-test/] [int-test.S] - Rev 828

Rev	Log message	Author	Age	Path
787	Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k: 2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com> Patch from R Diez <rdiezmail-openrisc@yahoo.de> * cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S, * except/except.S, ext/ext.S, flag/flag.S, fp/fp.S, * inst-set-test/inst-set-test.S, int-test/int-test.S, * mc-common/except-mc.S, uos/except-or32.S: Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero, and indeed it is not when simulating the or1200 Verilog core. * configure: Regenerated. * configure.ac: Updated version.	jeremybennett	4613d 22h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S
458	or1ksim testsuite updates	julius	5058d 03h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S
93	Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0.	jeremybennett	5308d 15h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5315d 15h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S