URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [toplevel.c] - Rev 461

Rev	Log message	Author	Age	Path
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5097d 18h	/openrisc/trunk/or1ksim/toplevel.c
385	Updates for Or1ksim 0.5.0rc2. * configure: Regenerated. * configure.ac: Minor tidy ups. Version changed to 0.5.0rc2. * debug/rsp-server.c (rsp_query): Simplified handling of "qTStatus" to indicate we just do not support tracing. * doc/or1ksim.texi <Configuring the Build>: No longer mandatory to specify the target. <Memory Configuration>: Warns about issues with memory controller. <Memory Controller Configuration>: Warns about issues with memory controller and advises not to use it. <Standalone Simulator>: Details for options with arguments updated. * NEWS: Updated for 0.5.0rc2. * peripheral/mc.c (mc_poc): Use constant MC_POC_VALID (mc_index): Ensure value is valid. * peripheral/mc-defines.h <MC_CE_VALID>: Defined. * testsuite/test-code-or1k/configure: Regenerated. * testsuite/test-code-or1k/configure.ac: Handle the case where target_cpu is not set. Version changed to 0.5.0rc2. * testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>: Definition corrected.	jeremybennett	5166d 01h	/openrisc/trunk/or1ksim/toplevel.c
202	Adding executed log in binary format capability to or1ksim	julius	5243d 00h	/openrisc/trunk/or1ksim/toplevel.c
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5661d 07h	/openrisc/trunk/or1ksim/toplevel.c