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[/] [openrisc/] [trunk/] [or1ksim/] [toplevel.c] - Rev 728

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Rev Log message Author Age Path
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5048d 12h /openrisc/trunk/or1ksim/toplevel.c
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5102d 00h /openrisc/trunk/or1ksim/toplevel.c
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5170d 07h /openrisc/trunk/or1ksim/toplevel.c
202 Adding executed log in binary format capability to or1ksim julius 5247d 06h /openrisc/trunk/or1ksim/toplevel.c
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5665d 12h /openrisc/trunk/or1ksim/toplevel.c

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