OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or_debug_proxy/] [Makefile] - Rev 822

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
682 Fixed error message in Makefile skrzyp 4650d 08h /openrisc/trunk/or_debug_proxy/Makefile
529 or_debug_proxy updates julius 4963d 22h /openrisc/trunk/or_debug_proxy/Makefile
498 or_debug_proxy updates to documentation and Makefile related to latest ftd2xx driver, julius 5009d 09h /openrisc/trunk/or_debug_proxy/Makefile
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5190d 02h /openrisc/trunk/or_debug_proxy/Makefile
94 Finally added byte reading to or_debug_proxy julius 5321d 22h /openrisc/trunk/or_debug_proxy/Makefile
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5560d 08h /openrisc/trunk/or_debug_proxy/Makefile
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5566d 09h /openrisc/trunk/or_debug_proxy/Makefile
39 Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update julius 5650d 09h /openrisc/trunk/or_debug_proxy/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.