URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [DebugUnitSC.h] - Rev 576

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	5078d 17h	/openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5430d 14h	/openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5440d 11h	/openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h