OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [Or1200MonitorSC.h] - Rev 462

Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4899d 14h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	4937d 21h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5020d 06h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5244d 11h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5251d 12h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5261d 09h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5348d 05h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5362d 07h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5381d 01h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5432d 11h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
6	Checking in ORPSoCv2	julius	5495d 00h	/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.