OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [Or1200MonitorSC.h] - Rev 52

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5367d 03h /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5381d 05h /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5399d 23h /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5451d 09h /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
6 Checking in ORPSoCv2 julius 5513d 22h /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.