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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [OrpsocAccess.h] - Rev 64

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63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5278d 19h /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5379d 17h /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5398d 11h /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5449d 22h /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
6 Checking in ORPSoCv2 julius 5512d 10h /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h

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