URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [OrpsocMain.h] - Rev 329

Rev	Log message	Author	Age	Path
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5464d 09h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5551d 05h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
6	Checking in ORPSoCv2	julius	5698d 00h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h