URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [OrpsocMain.h] - Rev 373

Rev	Log message	Author	Age	Path
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5192d 03h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5433d 09h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5520d 05h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
6	Checking in ORPSoCv2	julius	5667d 00h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h