URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [TraceSC.h] - Rev 517

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	5166d 00h	/openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5647d 11h	/openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h
6	Checking in ORPSoCv2	julius	5761d 10h	/openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h