URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [TraceSC.h] - Rev 178

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5580d 05h	/openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h
6	Checking in ORPSoCv2	julius	5694d 04h	/openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h