URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [UartSC.h] - Rev 678

Rev	Log message	Author	Age	Path
500	ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc ML501 simulation makefile update to allow custom ELFs to be specified	julius	5025d 04h	/openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	5087d 13h	/openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5449d 07h	/openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h
6	Checking in ORPSoCv2	julius	5682d 22h	/openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h