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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [GdbServerSC.cpp] - Rev 861

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861 sysc: include unistd.h

write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail		 stekern 4143d 08h /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 5051d 04h /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 5102d 11h /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5396d 00h /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5412d 22h /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp

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