URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [MemoryLoad.cpp] - Rev 179

Rev	Log message	Author	Age	Path
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5444d 04h	/openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5461d 02h	/openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5562d 00h	/openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp