URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [Modules.make] - Rev 178

Rev	Log message	Author	Age	Path
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5450d 16h	/openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5460d 13h	/openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5580d 05h	/openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make
6	Checking in ORPSoCv2	julius	5694d 04h	/openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make