URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [Or1200MonitorSC.cpp] - Rev 53

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5478d 13h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5479d 09h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5493d 11h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5512d 05h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5563d 16h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
6	Checking in ORPSoCv2	julius	5626d 04h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp