OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Rev 854

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified		 julius 5014d 00h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 5076d 08h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5145d 01h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5193d 07h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5194d 16h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5196d 21h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5398d 11h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5428d 05h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5438d 02h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5524d 22h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5539d 01h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5557d 19h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5609d 05h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
6 Checking in ORPSoCv2 julius 5671d 17h /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.