URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Rev 57

Rev	Log message	Author	Age	Path
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5519d 15h	/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5533d 18h	/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5552d 11h	/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5603d 22h	/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
6	Checking in ORPSoCv2	julius	5666d 10h	/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp