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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [TraceSC.cpp] - Rev 678

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462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 5079d 13h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5560d 23h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5612d 10h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5652d 04h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
6 Checking in ORPSoCv2 julius 5674d 22h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp

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