URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [TraceSC.cpp] - Rev 831

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4992d 15h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5474d 02h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5525d 12h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5565d 06h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
6	Checking in ORPSoCv2	julius	5588d 01h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp