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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [TraceSC.cpp] - Rev 178

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49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5580d 05h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5631d 15h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5671d 09h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
6 Checking in ORPSoCv2 julius 5694d 04h /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp

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