URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [TraceSC.cpp] - Rev 89

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5569d 20h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5621d 07h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5661d 01h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
6	Checking in ORPSoCv2	julius	5683d 19h	/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp