URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [UartSC.cpp] - Rev 462

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4905d 18h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5478d 09h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
6	Checking in ORPSoCv2	julius	5501d 03h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp