URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [UartSC.cpp] - Rev 518

Rev	Log message	Author	Age	Path
500	ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc ML501 simulation makefile update to allow custom ELFs to be specified	julius	4993d 13h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	5055d 21h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5628d 12h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
6	Checking in ORPSoCv2	julius	5651d 07h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp