URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [include/] [or1200_monitor_defines.v] - Rev 597

Rev	Log message	Author	Age	Path
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5031d 19h	/openrisc/trunk/orpsocv2/bench/verilog/include/or1200_monitor_defines.v