URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [mt48lc16m16a2.v] - Rev 636

Rev	Log message	Author	Age	Path
495	ORPSoC adding more accessor functions to Micron SDRAM model.	julius	5003d 08h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5129d 00h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5595d 10h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
6	Checking in ORPSoCv2	julius	5657d 22h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v