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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 413

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403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5045d 22h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5048d 04h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5098d 00h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5101d 00h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
348 First stage of ORPSoCv2 update - more to come julius 5101d 04h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5304d 09h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5388d 05h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5398d 21h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5460d 21h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6 Checking in ORPSoCv2 julius 5574d 20h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v

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