OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 456

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
456	ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default.	julius	4896d 22h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
449	ORPSoC - or1200_monitor.v additions enabling new experimental execution checks. Replace use of "clean-all" with "distclean" as make rule to clean things.	julius	4909d 18h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4916d 21h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4944d 22h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4951d 17h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	4953d 23h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5003d 19h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5006d 19h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
348	First stage of ORPSoCv2 update - more to come	julius	5006d 23h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5210d 04h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5294d 00h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5304d 16h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5366d 16h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6	Checking in ORPSoCv2	julius	5480d 15h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.