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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 833

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789 ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4616d 07h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
491 ORPSoC or1200_monitor update. julius 5014d 00h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5030d 16h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 5050d 20h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 5056d 16h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 5070d 11h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 5083d 06h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5090d 10h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5118d 11h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5125d 06h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5127d 12h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5177d 08h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5180d 08h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
348 First stage of ORPSoCv2 update - more to come julius 5180d 12h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5383d 16h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5467d 13h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5478d 05h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5540d 05h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6 Checking in ORPSoCv2 julius 5654d 04h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v

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