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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 188

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67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5371d 09h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5455d 05h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5465d 21h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5527d 21h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6 Checking in ORPSoCv2 julius 5641d 20h /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v

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