URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 355

Rev	Log message	Author	Age	Path
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5171d 07h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
348	First stage of ORPSoCv2 update - more to come	julius	5171d 11h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5374d 16h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5458d 12h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5469d 04h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5531d 04h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6	Checking in ORPSoCv2	julius	5645d 03h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v