URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Rev 55

Rev	Log message	Author	Age	Path
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5577d 20h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5639d 20h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
6	Checking in ORPSoCv2	julius	5753d 19h	/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v