URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 356

Rev	Log message	Author	Age	Path
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5193d 23h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5554d 21h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5606d 07h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5650d 08h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
6	Checking in ORPSoCv2	julius	5668d 20h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v