URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 46

Rev	Log message	Author	Age	Path
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5583d 19h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5627d 20h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
6	Checking in ORPSoCv2	julius	5646d 07h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v