OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [smii_phy.v] - Rev 856

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5165d 02h /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5561d 07h /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5580d 01h /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5631d 11h /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.