URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [uart_decoder.v] - Rev 365

Rev	Log message	Author	Age	Path
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5175d 13h	/openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5404d 03h	/openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v
6	Checking in ORPSoCv2	julius	5650d 10h	/openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v