OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [jp_vpi.c] - Rev 125

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5572d 17h /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/jp_vpi.c
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5652d 17h /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/jp_vpi.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.