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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Rev 277

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49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5562d 11h /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5577d 23h /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5657d 23h /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c

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