URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Rev 466

Rev	Log message	Author	Age	Path
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	5144d 11h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5557d 04h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5572d 16h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5652d 15h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c