URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.h] - Rev 46

Rev	Log message	Author	Age	Path
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5562d 08h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5642d 08h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h