URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [verilog/] [vpi_debug_defines.v] - Rev 168

Rev	Log message	Author	Age	Path
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5544d 06h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5624d 05h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v